Synchronous semiconductor memory device having an auto-precharge function

ABSTRACT

A semiconductor memory device according to the present invention having a plurality of memory banks, a row address strobe signal buffer, a column address strobe signal buffer and a column address generator and performing a data access operation in response to the burst length and latency information related to a system clock having a predetermined frequency, comprises a device for generating a signal which automatically precharges one memory bank of the memory banks in response to the row address strobe signal and the signal having the burst length and latency information after an address operation for the memory bank is completed.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device forprecharging a row chain, and particularly to a synchronous semiconductormemory device for automatically precharging the row chain.

The synchronous semiconductor memory device, which has been developedfor high speed operation, performs all operations required in accessingdata corresponding to a system clock (or a synchronous clock) ofconstant period supplied from externally. With the use of a mode setregister, such a synchronous semiconductor memory device sets variousoperation modes for determining the latency and burst length. Insemiconductor memory device, if a read or write operation of one row iscompleted, the activated row chain must be precharged in order toperform the read or write operation of another row.

As shown in FIG. 1, in a conventional semiconductor memory device, therow chain is precharged only when a precharge command is applied fromthe exterior of the device after one row has been activated. In asynchronous semiconductor memory device which operates with an externalsystem clock and performs the read/write operation in accordance withthe determined burst length and latency information, if the prechargeoperation of the row chain is performed in response to the prechargecommand applied from the exterior, as described above, undesirablyforcibly determines the proper point in time for precharging the rowchain and it is therefore difficult to realize an effective (i.e.reduction of the power consumption) precharge operation.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide asynchronous semiconductor memory device which is capable of internallyand automatically precharging a row chain.

It is another object of the present invention to provide the synchronoussemiconductor memory device having a reliable row chain prechargefunction.

To achieve the above objects, the semiconductor memory device accordingto the present invention includes a plurality of memory banks, a rowaddress strobe signal buffer, a column address signal buffer and acolumn address generator, and performs a data access operationcorresponding to the burst length and latency information related to asystem clock having a predetermined frequency. Also included is a devicewhich generates a precharge signal for automatically precharging onememory bank in response to the row address strobe signal, the signalhaving burst length and latency information after the address operationfor one memory bank is completed. Such a precharge signal is transferredto the row address strobe signal buffer, thereby allowing the rowaddress strobe signal buffer to precharge one memory bank.

BRIEF DESCRIPTION OF THE DRAWINGS

In the detailed description of the preferred embodiments of the presentinvention presented below, reference is made to the accompanyingdrawings, in which:

FIG. 1 is a timing diagram showing an operation according to aconventional precharge method;

FIG. 2 is a block diagram showing a construction for embodying anauto-precharge function according to the present invention;

FIG. 3 is a circuit diagram showing a RAS buffer according to thepresent invention as shown in FIG. 2;

FIG. 4 is a circuit diagram showing a burst/latency information signalgenerator according to the present invention as shown in FIG. 2.

FIG. 5 is a circuit diagram showing a burst/latency information signaldetector according to the present invention as shown in FIG. 2;

FIG. 6 is a circuit diagram showing a precharge signal generatoraccording to the present invention as shown in FIG. 2;

FIG. 7 is a timing diagram showing an operation according to an autoprecharge method of the present invention, assuming that a system clockis 66 MHz, burst length is 4 and CAS latency is 2; and

FIG. 8 is a timing diagram showing an operation according to an autoprecharge method of the present invention, assuming that the systemclock is 66 MHz, burst length is 2 and CAS latency is 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The construction of FIG. 2 required in realizing an auto prechargefunction according to the present invention includes a RAS buffer 100that receives a row address strobe signal RAS and then generates rowmaster clocks φR1 and φR2. A CAS buffer 200 receives a column addressstrobe signal CAS and then generates a column master clock φC whichdrives column related control circuits. A column address generator 300receives and buffers an address signal Ai to a CMOS level and thengenerates a plurality of column address signals (include CA10, CA11 andCA11) from the buffed address signal. An end of burst detector 400receives the column master clock φC and the counted column addresssignals and then generates a burst length detection signal COSI whichdetects the end state of the burst length. A timing controller 500receives the row master clocks φR1 and φR2 and then generates timingcontrol signals φS1DQ and φS2DQ. A burst/latency information signalgenerator 600 receives the burst length detection signal COSI, CASlatency information signal CLm (wherein "m" indicates the latencyvalue), WE activating information signal φWR (wherein WE is a writeenable signal) and a burst length signal SZn (wherein "n" indicates theburst length) and then generates a burst/latency information signalCOSA. A burst/latency information detector 700 receives the timingcontrol signals φS1DQ and φS2DQ, the burst/latency information signalCOSA and column address activating detection signals CA11A and CA11Agenerated from a precharge signal generator 800 and then generates aburst/latency information detection signal COSAP. The precharge signalgenerator 800 receives the column address signals CA10, CA11 and CA11,the burst length detection signal COSI and the burst/latency informationdetection signal COSAP and then generates and supplies precharge signalsΦAP1 and ΦAP2 to the RAS buffer 100 and the column address activatingdetection signals CA11A and CA11A to the burst/latency informationdetector 700.

FIG. 3 is a detailed circuit diagram showing the RAS buffer 100 of FIG.2, showing a minimum construction required in realizing the autoprecharge function according to the present invention. A P-channel inputtype differential amplifier 10 receives the reference voltage VREF andthe row address strobe signal RAS, amplifies the row address strobesignal RAS as much as the voltage difference therebetween and thenoutputs the internal column address strobe signal RAS which has beenshaped to a CMOS level. The output of the differential amplifier 10 isapplied to a transfer gate circuit 14 via three inverters 11. Theoperation of the transfer gate circuit 14 is controlled by the systemclock CLK. The signal passed through the transfer gate circuit 14 issupplied to a latch 15. The output of the latch 15 is converted and thenapplied to the PMOS transistor 17 and NMOS transistor 19 of an inverter16. The source of the PMOS transistor 17 is coupled to the power supplyvoltage Vcc, and the drain of the NMOS transistor 19 to the outputterminal of the inverter 16. The output of the NAND gate 13 whichreceives the system clock CLK and chip selection signal φCS is appliedto the gate of a PMOS transistor 18 connected between the drains of thePMOS transistor 17 and NMOS transistor 19, and the converted outputthereof is applied to the gate of a NMOS transistor 20 connected betweenthe NMOS transistor 19 and the substrate voltage Vss (ground voltage).The output of the inverter 16 is supplied to the pulse shaping circuit22 via two inverters 21.

The address signal SRA11 which selects the memory bank is applied to aNAND gate 29 via two inverters 24 and to a NAND gate 31 via an inverter27. The signal φWRCF which is activated after the write activatingsignal WE has been activated is applied to the NAND gates 29 and 31 viaan inverter 25 and to the NAND gates 32 and 34 via an inverter 26. Theoutput of the NAND gate 29 is applied to the NAND gates 32 and 33. Theoutput of the inverter 26 is applied to the NAND gates 33 and 35 via aninverter 30. The output of the NAND gate 31 is applied to the NAND gates34 and 35. The output of the pulse shaping circuit 22 is commonlysupplied to the NAND gates 32, 33, 34 and 35. The output of the NANDgate 32 is applied to the gate of a PMOS transistor 38 the source-drainpath of which is connected between the power supply voltage Vcc and afirst detection node 40. The output of the NAND gate 33 is applied viaan inverter 36 to the gate of an NMOS transistor 39 the drain-sourcepath of which is connected between the first detection node 40 and thesubstrate voltage Vss (ground voltage). The output of the NAND gate 34is applied to the gate of a PMOS transistor 41 the source-drain path ofwhich is connected between the power supply voltage Vet and a seconddetection node 43. The output of the NAND gate 35 is applied via aninverter 37 to the gate of an NMOS transistor 42 the drain-source pathof which is connected between the second detection node 43 and thesubstrate voltage Vss.

Between the first detection node 40 and the substrate voltage Vss isconnected the drain-source path of an NMOS transistor 46 having its gateconnected to the output of the NAND gate 1 which receives the powersupply voltage level detection signal φVCCH and the first prechargesignal ΦAP1 generated from the precharge signal generator 800 of FIG. 2.In the same way, between the second detection node 43 and the substratevoltage Vss is connected the drain-source path of the NMOS transistor 48having its gate connected to the output of the NAND gate 2 whichreceives the power supply voltage level detection signal φVCCH and thesecond precharge signal ΦAP2 generated from the precharge signalgenerator 800 of FIG. 2. The signals on the first and second detectionnodes 40 and 43 are respectively generated as the first and second rowmaster clocks φR1 and φR2 via the latches 45 and 47 and the inverters 49and 50. The row master clocks φR1 and φR2 are supplied to the rowrelated control circuits, that is, to the circuits which control thememory bank and drive the word lines therein.

FIG. 4 is a detailed circuit diagram showing the burst/latencyinformation signal generator 600 in FIG. 2. The burst length detectionsignal COSI generated from the end of the burst detector 400 in FIG. 2.is transferred to a latch 73 via the CMOS type transfer gate 63, latch65 and transfer gate 67. The n type electrode of the transfer gate 63and the p type electrode of the transfer gate 67 are controlled by thesystem clock CLK which has been converted by an inverter 61. The p typeelectrode of the transfer gate 63 and the n type electrode of thetransfer gate 67 are controlled by the system clock CLK which has beenpassed through the inverters 61 and 69. The source-drain path of a PMOStransistor 71 is connected between the power supply voltage Vcc and alatch 73, and the power supply voltage level detection signal φVCCH isapplied to the gate thereof. The burst length detection signal COSI isoutput as the burst/latency information signal COSA via a transfer gate64, and the output of the latch 73 is also outputted as theburst/latency information signal COSA via a transfer gate 68. Thetransfer gates 64 and 68 are controlled in response to the output of aNOR gate 62 which receives the CAS latency information signal CLm, theburst length signal SZn and the WE activating information signal φWR.The n type electrode of the transfer gate 64 and the p type electrode ofthe transfer gate 68 are directly coupled to the output of the NOR gate62, and the p type electrode of the transfer gate 64 and the n typeelectrode of the transfer gate 68 are controlled by the output of theNOR gate 62 which has been passed through an inverter 66. Theburst/latency information signal COSA generated via the transfer gates64 and 68 are transferred to the burst/latency information detector 700in FIG. 2.

FIG. 5 is a detailed circuit diagram showing the burst/latencyinformation detector 700 in FIG. 2. The burst/latency information signalCOSA is applied to a pulse shaping circuit 75, and the output of thepulse shaping circuit 75 is coupled to the gate of a PMOS transistor 76the source-drain path of which is connected between the power supplyvoltage Vcc and a node 74. The drain-source path of an NMOS transistor77 is coupled between the node 74 and the substrate voltage Vss. Thenode 74 is coupled to the input of a NAND gate 83 via a latch 78 and aninverter 79. Another input of the NAND gate 83 is coupled to the outputof the NAND gate 82 which outputs the logic comparison combination statebetween the column address activating detection signals CA11A and CA11Agenerated from the precharge generator 800 in FIG. 2 and the timingcontrol signals φS1DQ and φS2DQ generated from the timing controller 500in FIG. 2. The timing control signal φS1DQ and the column addressactivating detection signal CA11A are applied to a NAND gate 80, and thetiming control signal φS2DQ and the column address activating detectionsignal CA11A to a NAND gate 81. The outputs of the NAND gates 80 and 81are applied to a NAND gate 82. The output of a NAND gate 83 is generatedas the burst/latency information detection signal COSAP via the pulseshaping circuit 84, and the output of the pulse shaping circuit 84 isconnected to the gate of the NMOS transistor 77 via the pulse shapingcircuit 85.

FIG. 6 is a detailed circuit diagram showing the precharge signalgenerator 800 in FIG. 2. The column address signal CA11 and CA11 arerespectively applied to the NAND gates 86 and 87, and the column addresssignal CA10 is commonly applied to the NAND gates 86 and 87. The outputof the NAND gate 86 is generated as the column address activatingdetection signal CA11A via a transfer gate 90 and a latch 92, and theoutput of the NAND gate 87 is generated as the column address activatingdetection signal CA11A via a transfer gate 91 and a latch 93. Thetransfer gates 90 and 91 are controlled by the output of the pulseshaping circuit 88 which receives the burst length detection signalCOSI. The p type electrodes of the transfer gates 90 and 91 are directlycoupled to the output of the pulse shaping circuit 88, and the n typeelectrodes thereof are coupled to the output of the pulse shapingcircuit 88 which has been passed through an inverter 89. The output ofthe latches 92 and 93 are respectively applied to the NAND gates 94 and95 which commonly receive the burst/latency information detection signalCOSAP. The outputs of the NAND gates 94 and 95 are respectivelygenerated as the first and second precharge signals ΦAP1 and ΦAP2 viathe inverters 96 and 97.

Referring to the timing diagram of FIG. 7, the auto precharge operationaccording to the present invention will now be described, assuming thatthe frequency of the system clock CLK is 66 MHz, the burst length is 4and the CAS latency value is 2. First, the auto precharge process in aread cycle which starts from time t1 will be described. At time t1, ifthe row address strobe signal RAS is activated to a low state, the rowaddress is latched. Referring now to FIG. 3, the output of thedifferential amplifier 10 becomes a logic high state by the activatedrow address strobe signal RAS, and if the system clock CLK is in thelogic low state, the signal of the logic low state is applied to thegate of the PMOS transistor 17 of the inverter 16. The system clock CLKis rendered to the logic high state (clock 1), the transfer gate circuit14 turns off and the P-channel transistor 18 of the inverter 16 turns on(the chip selection signal φCS maintains at the logic high state inoperation), with the result of that the output of the inverter 16 isrendered to the logic high state. Thus, the output of the pulse shapingcircuit 22 becomes a short pulse of logic high state and then is appliedto the NAND gates 32, 33, 34 and 35, thus activating those NAND gates.Since the signal φWRCF is in the logic low state (because the writeactivating signal WE is inactivated.), if the bank selection signalSRA11 is rendered to the logic high state, the row master clock φR2 oflogic high state is generated by the PMOS transistor 41 which has beenturned on by the output of the NAND gate 34 of logic low state. Assumingthat this row master clock φR2 is supplied to the row related circuitsfor the second memory bank (the present invention is applied to thesemiconductor memory device having two memory banks), in as much as thebank selection signal SRA11 of logic high state is input, the row masterclock φR2 maintains at the logic high state by the latch 47 as shown inFIG. 7. On the contrary, if the bank selection signal SRA11 of logic lowstate is inputted, the row master clock φR1 of logic high state insteadof the row master clock φR2 is outputted, to activate the row relatedcircuits for the first memory bank.

At time t2, as the column address strobe signal CAS is activated, thecolumn address CAi is latched. Whether to auto precharge or not isdetermined by using the logic state of the column address signals CA10and CA11. That is, as shown in FIG. 7, if the column address signalsCA10 and CA11 are in the logic high state, it is determined to performthe auto precharge operation.

If m is 3 in the CAS latency information signal CLm (which becomes logichigh state when the CAS latency is "3") and n is 2 in the burst lengthsignal SZn (which becomes logic high state when the burst length is "2")in FIG. 4, since the CAS latency is "2", and the burst length is "4" inFIG. 7, both CL3 and SZ2 are in the logic low state. Also, being in aread cycle, WE activating information signal φWR remains at the logiclow state. Thereby, the transfer gate 64 turns on and the transfer gate68 turns off, so that the burst length detection signal COSI which hasbeen activated at time 13 is generated as the burst/latency informationsignal COSA of logic high state via the transfer gate 64 (hereinafterreferred to as a "direct transfer path 601"). Referring to FIG. 5, theburst/latency information signal COSA of logic high state is passedthrough the pulse shaping circuit 75 and then is applied to the gate ofthe PMOS transistor 76 as a short pulse of logic low state. Then, theshort pulse of logic high state is applied from the node 74 to the NANDgate 83 via the latch 78 and the inverter 79. Since the timing controlsignal φS1DQ and the column address activating detection signal CA11Aare in the logic low state and the timing control signal φS2DQ and thecolumn address activating detection signal CA11A are in the logic highstate, the output of the NAND gate 82 to be applied to the NAND gate 83is rendered to the logic high state. Hence, the output of the NAND gate83 becomes the signal of logic low state. Consequently, the signal oflogic low state is outputted through the pulse shaping circuit 84 as theburst/latency information detection signal COSAP of logic high state ofthe short pulse, as shown in FIG. 7. The pulse shaping circuit 85 whichforms the feedback loop between the pulse shaping circuit 84 and theNMOS transistor 77 detects that the burst/latency information detectionsignal COSAP of logic high state has been changed to the logic low stateand then applies the short pulse signal of logic high state to the gateof the NMOS transistor 77, thus serving to inactivate the burst/latencyinformation detection signal COSAP.

Referring to FIG. 6, the column address activating detection signalsCA11A and CA11A are respectively generated in the logic low and highstates from the latches 92 and 93 by the column address signals CA10 andCA11 of logic high state. The transfer gates 90 and 91 are turned on bythe short pulse of logic low state which responds to the burst lengthdetection signal COSI of logic high state. Thus, the latches 92 and 93keep the logic state of the stored column address signal CA11 by theburst length detection signal COSI. Since the burst/latency informationdetection signal COSAP generated from FIG. 5 is in the logic high state,the first precharge signal ΦAP1 is rendered to the logic high state(inactive state) and the second precharge signal ΦAP2 to the logic lowstate (active state).

Referring to FIG. 3, the first and second precharge signals ΦAP1 andΦAP2 respectively generated in the logic high and low states from FIG. 6are respectively applied to the NAND gates 1 and 2. Accordingly, thesignal of logic low state is applied to the gate of the NMOS transistor46 connected between the detection node 40 and the substrate voltageVss, and the signal of logic high state to the gate of the NMOStransistor 48 connected between the detection node 43 and the substratevoltage Vss. As a result, the row master clock φR2 which has been keptat the logic high state is changed to the logic low state by the turn onof the pull-down NMOS transistor 48, as shown in FIG. 6. That is, as therow master clock φR2 which has been activated to drive the second memorybank (e.g. the driving for the read operation) is inactivated, thesecond memory bank automatically performs the precharge operation. Theprecharge operation of the second memory bank (not shown) is performedin a well known way, and such will not be described in the preferredembodiment of the present invention. In the prior art, the prechargecommand must be forcibly applied from the external in order to prechargeany memory bank after the read operation of one cycle is completed.

In the auto precharge operation for the write cycle which starts at timet4, since WE activating information signal φWR becomes logic high ratein FIG. 4 as the write activating signal WE is activated to the logiclow state at time t5, the burst/latency information signal COSA isgenerated after being delayed as much as one clock of the system clockCLK from the burst length detection signal COSI, as shown in FIG. 7.That is, as the clock 14 of the system clock CLK is changed to the logiclow state, the burst length detection signal COSI is passed through thetransfer gate 63 to be stored at the latch 65 (at this time, thetransfer gate 67 is turned off.), and as the clock 15 of the systemclock CLK is changed to the logic high state, the signal stored at thelatch 65 is passed through the transfer gate 67, the latch 73 and thetransfer gate 68 (hereinafter referred to as a "delay path 602") andthen is generated as the burst/latency information signal COSA which isdelayed as much as one clock from the burst length detection signalCOSI. The remaining steps are equal to the case of the aforementionedread cycle, and the auto precharge operation for the second memory bankis performed as the row master clock φR2 which activates the secondmemory bank at time t6 is inactivated to the logic low state by thesecond precharge signal ΦAP2 of logic low state.

Referring to FIG. 8 showing the auto precharge method according to thepresent invention in case of the burst length being 2, as the burstlength signal SZn (n=2) is in the logic high state and the output of theNOR gate 62 is thus rendered to the logic low state, the burst lengthdetection signal COSI is transferred via the delay path 602.Consequentially, the burst/latency information signal COSA is generatedafter being delayed as much as one clock of the system clock CLK fromthe burst length detection signal COSI. In addition, since theburst/latency information signal COSA which has been outputted as theshort pulse through the pulse shaping circuit 75 corresponds to thelogic state of the timing control signal φS2DQ which is generated withthe lapse of a predetermined time from the activation time point of RASin order to pass through the NAND gate 83, if the timing control signalφS1DQ is in the logic high state, the burst/latency informationdetection signal COSAP is rendered to the logic high state. The dottedline in FIG. 8 shows the case that RAS information does not control theauto precharge. As a result, FIG. 8 shows the fact that theburst/latency information detection signal COSAP required in generatingthe auto precharge signals ΦAP1 and ΦAP2 is influenced by theinformation related to RAS as well as the information related to theburst length and CAS latency.

Thus, since the auto precharge signal according to the present inventionis generated corresponding to information related to the burst lengthand latency used in the synchronous semiconductor memory device, as wellas the information related to the row and column address strobe signalsRAS and CAS that are typically used in data access operations insemiconductor memory devices, an effective and reliable auto prechargefunction can be achieved.

The above-described embodiment of the present invention utilizes thecircuit constructions as shown in FIGS. 4 to 7 in order to reflect theinformation required in generating the auto precharge signal, however,the auto precharge signal according to the present invention can begenerated with another circuit construction.

What is claimed is:
 1. A semiconductor memory device using row andcolumn address strobe signals comprising:a plurality of memory bankseach including a plurality of memory cells; and means for generating asignal which automatically precharges at least one memory bank of saidmemory banks in response to receiving a signal which corresponds to saidrow and column address strobe signals after an address operation forsaid memory bank is completed, said address operation activating atleast one of said plurality of memory cells.
 2. A semiconductor memorydevice which performs a data access operation in response to burstlength and latency information related to a system clock having apredetermined frequency, said semiconductor memory device comprising:aplurality of memory banks; a row address strobe signal buffer; a columnaddress strobe signal buffer; a column address generator; and means forgenerating a signal which automatically precharges one memory bank ofsaid memory banks in response to said column address strobe signal andsaid burst length and latency information after an address operation forsaid memory bank is completed.
 3. A semiconductor memory device whichperforms a data access operation in response to burst length and latencyinformation related to a system clock having a predetermined frequency,said semiconductor memory device comprising:a plurality of memory bankseach including a plurality of memory cells; a circuit generating a rowmaster clock for driving row related control circuits which are includedin one memory bank of said memory banks in response to a row addressstrobe signal applied externally and a bank selection signal; and acircuit which generates said row master clock, said circuit beingsupplied with a signal generated in response to said row address strobesignal and said burst length and latency information after an addressoperation for one memory bank of said memory banks is completed, saidaddress operation activating at least one of said plurality of memorycells.
 4. A semiconductor memory device which performs a data accessoperation in response to burst length and latency information related toa system clock having a predetermined frequency, said semiconductormemory device comprising:a plurality of memory banks including aplurality of memory cells; a row master clock generating circuit whichgenerates a row master clock for driving row related control circuitsthat are included in one memory bank of said memory banks in response toa row address strobe signal applied externally and a bank selectionsignal; a column master clock generating circuit which receives a columnaddress strobe signal externally and then generates a column masterclock for driving column related control circuits which are included insaid one memory bank of said memory banks, a column address generatingcircuit which receives address signals externally and then generatescolumn address signals; and a circuit which generates said row masterclock, said circuit being supplied with a signal generated in responseto said row address strobe signal and said burst length and latencyinformation after an address operation for one memory bank of saidmemory banks is completed, said address operation activating at leastone of said plurality of memory cells.
 5. A semiconductor memory devicehaving a plurality of memory banks including a plurality of memorycells, and a circuit generating a row master clock for driving rowrelated control circuits which are included in one memory bank of saidmemory banks in response to a row address strobe signal appliedexternally and a bank selection signal, a circuit receiving acolumn.[.a.]. address strobe signal externally and then generating acolumn master clock for driving column related control circuits whichare included in one memory bank of said memory banks, and a circuitreceiving address signals externally and then generating column addresssignals and performing a data access operation in response to burstlength and latency information related to a system clock having apredetermined frequency, said semiconductor memory devicecomprising:means for generating a timing control signal corresponding tosaid row master clock; a circuit which receives said timing controlsignal and said burst length and latency information and then generatessaid column address strobe signal and an information detection signalderived from said burst length and latency information; and means fortransferring to a circuit which generates said row master clock aprecharge signal responding to a signal which contains said burstlength, a column address signal and said information detection signal..Iadd.
 6. A method of operating a semiconductor memory device responsiveto row and column address strobe signals, comprising the stepsof:addressing at least one memory cell in a bank of memory cells; andgenerating a signal which automatically precharges the bank of memorycells in response to receiving a signal which corresponds to the row andcolumn address strobe signals after said addressing step iscompleted..Iaddend..Iadd.7. A method of operating a semiconductor memorydevice, comprising the steps of: generating a column address strobesignal; addressing at least one memory cell in a bank of memory cells;and generating a signal which automatically precharges the bank ofmemory cells in response to the column address strobe signal and burstlength and latency information which is related to a system clock havinga predetermined frequency, after said addressing step has beencompleted..Iaddend..Iadd.8. A method of operating a semiconductor memorydevice, comprising the steps of: addressing at least one memory cell ina bank of memory cells; generating a row master clock signal from rowrelated control circuits electrically coupled to the bank of memorycells, in response to a row address strobe signal and a bank selectionsignal; and generating a signal to precharge the bank of memory cells,in response to the row address strobe signal and burst length andlatency information which is related to a system clock having apredetermined frequency, after said addressing step has beencompleted..Iaddend..Iadd.9. The method of claim 8, further comprisingthe steps of:generating a column master clock signal in response to acolumn address strobe signal; and generating a column address whichcontains bank selection information and autoprecharge information, inresponse to an address..Iaddend..Iadd.10. The method of claim 8, furthercomprising the steps of: generating a timing control signal in responseto the row master clock signal; generating a burst/latency informationdetection signal in response to the timing controlsignal..Iaddend..Iadd.11. The method of claim 10, wherein a timing ofsaid step of generating a burst/latency information detection signalvaries depending on a value of the burst length and a value of thelatency information; and wherein said step of generating a signal toprecharge the bank of memory cells is performed in response to theburst/latency information detection signal..Iaddend..Iadd.12. A methodof operating a synchronous DRAM memory device during a burst readingmode, comprising the steps of: activating a row master clock signalduring a first time interval; generating a column address in response toa column address strobe signal; reading data from the memory deviceduring the first time interval, in response to the column address strobesignal; generating a precharge signal during the first time interval, inresponse to the column address; deactivating the row master clock signalin response to the precharge signal; and precharging the memory deviceduring a second time interval following the first time interval, inresponse to the precharge signal..Iaddend..Iadd. The method of claim 12,further comprising the steps of:activating a column master clock signalduring the first time interval, in response to the column address strobesignal; and generating a burst length detection signal during the firsttime interval, in response to the column address and the column masterclock signal; and wherein said step of generating a precharge signalcomprises generating a precharge signal during the first time interval,in response to the column address and the burst length detectionsignal..Iaddend..Iadd.14. The method of claim 13, further comprising thesteps of: generating a column address activating detection signal, inresponse to the column address and the burst length detection signal;and generating a timing control signal, in-sync with said step ofactivating a row master clock signal..Iaddend..Iadd.15. The method ofclaim 14, further comprising the steps of: generating a burst/latencyinformation signal, in response to the burst length detection signal;and generating a burst latency information detection signal, in responseto the burst/latency information signal, the timing control signal andthe column address activating detection signal..Iaddend..Iadd.16. Themethod of claim 15, wherein said step of generating a precharge signalcomprises generating a precharge signal during the first time interval,in response to the column address, the burst length detection signal andthe burst latency information detection signal..Iaddend..Iadd.17. Themethod of claim 12, wherein said step of generating a precharge signaloverlaps in time with said step of reading data from the memorydevice..Iaddend..Iadd.18. A method of operating a synchronous DRAMmemory device during a burst mode having a burst length and a columnaddress strobe latency, comprising the steps of:activating a row masterclock signal during a first time interval; activating a word lineelectrically coupled to a row of memory cells in the memory device inresponse to the row master clock signal; generating a column address inresponse to a column address strobe signal; generating a burst lengthsignal; generating, in response to the column address, a prechargesignal at a first point in the first time interval if the burst lengthdoes not correspond to the burst length signal and at a second point inthe first time interval if the burst length corresponds to the burstlength signal; deactivating the row master clock signal in response tothe precharge signal; and precharging the memory device in response tothe precharge signal..Iaddend..Iadd.19. The method of claim 18, whereinsaid step of precharging the memory device includes the step ofdeactivating the word line..Iaddend..Iadd.20. The method of claim 18,wherein the second point in the first time interval is delayed in timerelative to the first point in the first timeinterval..Iaddend..Iadd.21. The method of claim 18, further comprisingthe step of generating a latency signal; and wherein said step ofgenerating a precharge signal comprises generating, in response to thecolumn address, a precharge signal at the first point in the first timeinterval if the burst length corresponds to the burst length signal andthe latency signal corresponds to the column address strobelatency..Iaddend..Iadd.22. The method of claim 21, wherein said step ofgenerating a precharge signal comprises generating, in response to thecolumn address, a precharge signal at the second point in the first timeinterval if the burst length does not correspond to the burst lengthsignal or if the column address strobe latency does not correspond tothe latency signal..Iaddend..Iadd.23. The method of claim 22, whereinthe second point in the first time interval is delayed in time relativeto the first point in the first time interval..Iaddend..Iadd.24. Amethod of operating a synchronous DRAM memory device during a burstmode, comprising the steps of:activating a row master clock signalduring a first time interval; activating a word line electricallycoupled to a row of memory cells in the memory device in response to therow master clock signal; writing data to the memory device during awrite time interval; reading data from the memory device during a readtime interval; generating a column address in response to a columnaddress strobe signal; generating, in response to the column address, aprecharge signal at a first point in the first time interval if the readtime interval overlaps the first time interval and at a second point inthe first time interval if the write time interval overlaps the firsttime interval; deactivating the row master clock signal in response tothe precharge signal; and precharging the memory device in response tothe precharge signal..Iaddend..Iadd.25. The method of claim 24, whereinsaid step of precharging the memory device comprises the step ofdeactivating the word line..Iaddend..Iadd.26. The method of claim 24,wherein the second point in the first time interval is delayed in timerelative to the first point in the first timeinterval..Iaddend..Iadd.27. A synchronous DRAM memory device,comprising:a row address strobe buffer which activates a row masterclock signal during a first time interval in response to a row addressstrobe signal and deactivates the row master clock signal at an end ofthe first time interval in response to a precharge signal; a memorybank, responsive to the row master clock signal; and a precharge signalgenerator which generates the precharge signal during the first timeinterval, in response to a column address..Iaddend..Iadd.28. The memorydevice of claim 27, wherein said precharge signal generator generatesthe precharge signal in response to the column address and a burstlength detection signal..Iaddend..Iadd.29. The memory device of claim27, further comprising an end-of-burst detector which generates a burstlength detection signal in response to a column master clock signal; andwherein said precharge signal generator generates the precharge signalin response to the column address and a burst length detectionsignal..Iaddend..Iadd.30. The memory device of claim 29, furthercomprising:a burst/latency information signal generator which generatesa burst/latency information signal in response to burst length detectionsignal and at least one of a latency signal, a write enable activatinginformation signal and a burst length signal; and a timing controlcircuit which generates a timing control signal in response to the rowmaster clock signal..Iaddend..Iadd.31. The memory device of claim 30,further comprising a burst/latency information detector which generatesa burst latency information detection signal in response to the timingcontrol signal and the burst/latency information signal; and whereinsaid precharge signal generator generates the precharge signal inresponse to the column address, the burst length detection signal andthe burst latency information detection signal..Iaddend..Iadd.32. Thememory device of claim 31, wherein said precharge signal generatorgenerates a column address activating detection signal; and wherein saidburst/latency information detector generates a burst latency informationdetection signal in response to the timing control signal, theburst/latency information signal and the column address activatingdetection signal..Iaddend..Iadd.33. A synchronous memory device,comprising:an address generator which generates a first control signalin response to an auto-precharge command signal; a burst detector whichgenerates an end of burst signal by detecting a timing of an end of aburst operation; and an auto-precharge signal generator which generatesan auto-precharge signal to automatically precharge at least one memorybank of a plurality of memory banks in response to the end of burstsignal and the first control signal..Iaddend..Iadd.34. A synchronousmemory device, comprising: an address generator which generates a firstcontrol signal in response to an auto-precharge command signal which isprovided in sync with an external clock signal; a burst detector whichgenerates an end of burst signal by detecting a timing of an end of aburst operation; an auto-precharge signal generator which generates anauto-precharge signal to automatically precharge at least one memorybank of a plurality of memory banks in response to the end of burstsignal and the first control signal; and a row addressing circuit whichdesignates a row in a memory array in accordance with a given rowaddress combination, and designates a precharging row in response to theauto-precharge signal..Iaddend..Iadd. A semiconductor memory devicewhich performs a burst operation according to a predetermined latencyinformation signal and a burst length information signal which areprovided in-sync with an external clock signal, comprising:a pluralityof memory banks; a burst detector which generates an end of burst signalby detecting a timing of an end of the burst operation; and anauto-precharge signal generator which generates an auto-precharge signalto automatically precharge at least one of said plurality of memorybanks in response to the end of burst signal and the latency informationsignal and the burst length information signal..Iaddend..Iadd.36. Asemiconductor memory device which performs a burst operation accordingto a predetermined latency and burst length information set by a user,in-sync with an external clock signal, said semiconductor memory devicecomprising: a plurality of memory banks; a burst detector whichgenerates an end of burst signal by detecting a timing of the end ofsaid burst operation; an auto-precharge signal generator which generatesan auto-precharge signal to automatically precharge at least one memorybank of said plurality of memory banks in response to the end of burstsignal and the predetermined latency and the burst length information,and wherein said auto-precharge signal is enabled when the burstoperation is completed; and a row addressing circuit which designates arow in the at least one memory bank in accordance with a given rowaddress combination, and designates a precharging row in response to theauto-precharge signal..Iaddend..Iadd. The semiconductor memory device ofclaim 36, wherein the row addressing circuit designates a row in saidplurality of memory banks in accordance with a given row addresscombination and precharges a row in at least one of said plurality ofmemory banks in response to the auto-precharge signal and a bankselection signal..Iaddend.